Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4782033
SERIAL NO

06928893

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A process for the production of highly integrated circuits contaiining p-and n-channel MOS transistors including gate electrodes which consist of a doped double layer of polysilicon and metal silicide. The gates are doped with boron and are produced by diffusion from the metal silicide layer which has previously been doped with boron by ion implantation into the undoped polysilicon layer. The metal silicide layer preferably consisting of tantalum silicide is provided with a masking layer consisting of SiO.sub.2, and the structuring of the boron-doped silicide gate and the masking layer is carried out after the boron atoms have been diffused in. The process serves to safely avoid undesired boron penetration effects which considerably influence the short channel properties of the transistors. The process is used for the production of CMOS-circuits having a high packing density.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
SIEMENS AKTIENGESELLSCHAFTMUNICH7350

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gierisch, Heike Unterschleissheim, DE 1 24
Neppl, Franz Munich, DE 22 615

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Societe pour l'Etude et la Fabrication des Circuits Integres Speciaux (EFCIS) (1)
* 4593454 Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation 55 1984
 
SIEMENS AKTIENGESELLSCHAFT (2)
* 4525378 Method for manufacturing VLSI complementary MOS field effect circuits 11 1984
* 4640844 Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon 17 1985
 
SAMSUNG ELECTRONICS CO., LTD. (1)
* 4443930 Manufacturing method of silicide gates and interconnects for integrated circuits 64 1982
 
BELL TELEPHONE LABORATORIES, INCORPORATED (2)
* 4450620 Fabrication of MOS integrated circuit devices 34 1983
* 4555842 Method of fabricating VLSI CMOS devices having complementary threshold voltages 42 1984
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6362056 Method of making alternative to dual gate oxide for MOSFETs 12 2000
 
SEIKO EPSON CORPORATION (1)
* 5612557 Semiconductor device having an inter-layer insulating film disposed between two wiring layers 17 1995
 
LUCENT TECHNOLOGIES INC. (1)
* 6313021 PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance 4 1999
 
XEROX CORPORATION (1)
* 4859278 Fabrication of high resistive loads utilizing a single level polycide process 15 1988
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (2)
* 5541131 Peeling free metal silicide films using ion implantation 36 1991
* 5840607 Method of forming undoped/in-situ doped/undoped polysilicon sandwich for floating gate application 39 1996
 
SAMSUNG ELECTRONICS CO., LTD. (2)
* 5013686 Method of making semiconductor devices having ohmic contact 16 1988
* 5837605 Manufacturing method of transistors 5 1995
 
SK HYNIX INC. (2)
* 9368586 Transistor with recess gate and method for fabricating the same 0 2012
* 2014/0001,541 TRANSISTOR WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME 2 2012
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
* 5604157 Reduced notching of polycide gates using silicon anti reflection layer 31 1995
 
HITACHI, LTD. (1)
* 5081052 ROM and process for producing the same 40 1989
 
INFINEON TECHNOLOGIES AG (1)
* 5190888 Method for producing a doped polycide layer on a semiconductor substrate 23 1991
 
NEC CORPORATION (2)
* 7247910 MOSFET formed on a silicon-on-insulator substrate having a SOI layer and method of manufacturing 7 2003
* 2005/0098,831 Semiconductor device and it's manufacturing method 1 2003
 
AT&T LABS, INC. (1)
* 5278096 Transistor fabrication method 15 1991
 
UNITED MICROELECTRONICS CORP. (2)
* 5472896 Method for fabricating polycide gate MOSFET devices 38 1994
* 5576228 Method for fabricating polycide gate MOSFET devices 24 1995
 
PS4 LUXCO S.A.R.L. (2)
* 6800543 Semiconductor device having a low-resistance gate electrode 12 2002
* 2003/0170,942 Semiconductor device having a low-resistance gate electrode 3 2002
 
INTERSIL CORPORATION (1)
* 4945070 Method of making cmos with shallow source and drain junctions 37 1989
 
LONGITUDE SEMICONDUCTOR S.A.R.L. (2)
* 7078777 Semiconductor device having a low-resistance gate electrode 0 2004
* 2005/0020,045 Semiconductor device having a low-resistance gate electrode 0 2004
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
* 6555887 Semiconductor device with multi-layer interconnection 0 1999
 
KABUSHIKI KAISHA TOSHIBA (2)
* 5464789 Method of manufacturing a CMOS semiconductor device 18 1993
* 5612245 Method of manufacturing CMOS device 7 1995
 
PROMOS TECHNOLOGIES INC. (2)
* 6770551 Methods for manufacturing semiconductor and CMOS transistors 2 2002
* 2003/0139,038 Method for manufacturing semiconductor element 0 2002
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
* 5652183 Method for fabricating semiconductor device containing excessive silicon in metal silicide film 10 1995
* Cited By Examiner