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Abstract

A one-chip, integrated-circuit, 32-bit bipolar arithmetic-logic unit (ALU) capable of performing complex operations on selected one, two, three, or four 8-bit bytes or selected contiguous bits of the operands in a single clock cycle. The ALU has three 32-bit inputs consisting of two data word operands and a mask; operand with shifters provided at one of the operand input, the mask input and at the ALU output so that three operands can be simultaneously received, shifted, masked, combined, and the result shifted in a single instruction cycle. Bit positions which are not selected to take part in an ALU operation pass unaffected to the outputs from one of the data word inputs. A swap multiplexer is present at the data word inputs to afford interchanging of these inputs before processing by the ALU. A moving arithmetic cell is employed within the ALU which can be appended to the selected high-order byte during a multiplication operation and the ALU is composed of sixteen two-bit arithmetic cells which generate four conditional sums to which a last minute correction is made based on the carry in to the cell from the adjoining cell. A one-bit upshift or a two-bit downshift of the result can be made during the same clock cycle to implement the division and multiplication algorithms used by the ALU. A terminal pin is provided to permit selection of a borrow or a carry made to be utilized during subtractions.

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