Method and device for regenerating the integrity of the bit rate in a plesiosynchronous system
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United States of America Patent
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Nov 15, 1988
Grant Date -
N/A
app pub date -
Jan 7, 1987
filing date -
Jan 10, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The network of the invention comprises, in the transmitter, a 'marker' generator which inserts bits of a cyclical sequence into the binary data flow and, in the receiver, a marker processing circuit by which it is possible to identify the start of the marker cycle in order to re-justify the useful data signal in accordance with the detection of this start of a cycle.
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