Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
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United States of America Patent
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Nov 22, 1988
Grant Date -
N/A
app pub date -
Oct 5, 1987
filing date -
Oct 5, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36). The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts.
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