US Patent No: 4,786,904

Number of patents in Portfolio can not be more than 2000

Electronically programmable gate array having programmable interconnect lines

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Abstract

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An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ZORAN CORPORATIONSUNNYVALE, CA8

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Graham, III Hatch Santa Clara, CA 2 178
Seltz, Daniel Mountain View, CA 3 185

Cited Art Landscape

Patent Info (Count) # Cites Year
 
SIEMENS NIXDORF INFORMATIONSSYSTEME AG (1)
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ZILOG, INC. (1)
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KABUSHIKI KAISHA TOSHIBA (1)
* 4,631,686 Semiconductor integrated circuit device 56 1984
 
ZORAN CORPORATION (1)
* 4,590,589 Electrically programmable read only memory 81 1982
 
XILINX, INC. (1)
* 4,642,487 Special interconnect for configurable logic array 416 1984
 
RCA CORPORATION, A CORP. OF DE (2)
* 4,612,459 Programmable buffer selectively settable to operate in different modes 26 1984
* 4,596,938 Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs 29 1984
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
The Mitre Corporation (1)
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AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (2)
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CADENCE DESIGN SYSTEMS, INC. (17)
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* 5,657,241 Routing methods for use in a logic emulation system 38 1995
* 5,612,891 Hardware logic emulation system with memory capability 63 1995
* 5,644,515 Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation 39 1995
* 5,841,967 Method and apparatus for design verification using emulation and simulation 77 1996
* 5,884,066 Method and apparatus for a trace buffer in an emulation system 18 1997
* 5,960,191 Emulation system with time-multiplexed interconnect 88 1997
* 5,970,240 Method and apparatus for configurable memory emulation 54 1997
6,421,251 Array board interconnect system and method 31 1998
* 6,134,516 Simulation server system and method 101 1998
* 6,026,230 Memory simulation system and method 81 1998
6,389,379 Converification system and method 157 1998
* 6,058,492 Method and apparatus for design verification using emulation and simulation 45 1998
6,377,912 Emulation system with time-multiplexed interconnect 73 1999
6,842,729 Apparatus for emulation of electronic systems 14 2002
 
FREESCALE SEMICONDUCTOR, INC. (1)
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Logic Devices, Inc. (3)
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ALTERA CORPORATION (10)
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* 5,485,103 Programmable logic array with local and global conductors 190 1994
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6,759,870 Programmable logic array integrated circuits 2 2003
 
XILINX, INC. (3)
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* 5,744,979 FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses 109 1996
 
QUICKTURN DESIGN SYSTEMS, INC. (8)
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* 5,329,470 Reconfigurable hardware emulation system 139 1993
* 5,812,414 Method for performing simulation using a hardware logic emulation system 47 1996
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* 5,734,581 Method for implementing tri-state nets in a logic emulation system 19 1996
* 5,963,735 Hardware logic emulation system 32 1997
6,377,911 Apparatus for emulation of electronic hardware system 22 1999
 
Actel Corporation (24)
4,873,459 Programmable interconnect architecture 371 1988
* 5,015,885 Reconfigurable programmable interconnect architecture 62 1989
* 5,073,729 Segmented routing architecture 124 1990
* 5,132,571 Programmable interconnect architecture having interconnects disposed above function modules 200 1990
* 5,365,165 Testability architecture and techniques for programmable interconnect architecture 25 1992
* 5,341,043 Series linear antifuse array 15 1992
* 5,341,092 Testability architecture and techniques for programmable interconnect architecture 30 1992
* 5,440,245 Logic module with configurable combinational and sequential blocks 104 1993
* 5,432,441 Testability architecture and techniques for programmable interconnect architecture 18 1993
* 5,485,031 Antifuse structure suitable for VLSI application 109 1993
* 5,451,887 Programmable logic module and architecture for field programmable gate array device 98 1994
* 5,477,165 Programmable logic module and architecture for field programmable gate array device 31 1994
* 5,610,534 Logic module for a programmable logic device 7 1995
5,510,730 Reconfigurable programmable interconnect architecture 120 1995
* 5,570,041 Programmable logic module and architecture for field programmable gate array device 41 1995
* 6,111,302 Antifuse structure suitable for VLSI application 28 1995
* 5,606,267 Programmable logic module and architecture for field programmable gate array device 32 1995
* 5,600,265 Programmable interconnect architecture 120 1995
6,160,420 Programmable interconnect architecture 38 1996
* 5,780,323 Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug 39 1996
* 5,781,033 Logic module with configurable combinational and sequential blocks 20 1996
* 5,698,992 Programmable logic module and architecture for field programmable gate array device 27 1996
7,830,173 Method and apparatus for universal program controlled bus architecture 3 2009
8,289,047 Architecture and interconnect scheme for programmable logic circuits 0 2010
 
MENTOR GRAPHICS CORPORATION (10)
* 5,377,124 Field programmable printed circuit board 46 1989
* 5,371,390 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits 79 1992
* 5,321,322 Programmable interconnect architecture without active devices 40 1993
* 5,544,069 Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components 35 1993
* 5,400,262 Universal interconnect matrix array 58 1993
* 5,504,354 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits 34 1994
* 5,654,564 Interconnect structure with programmable IC for interconnecting electronic components, including circuitry for controlling programmable IC 53 1996
* 5,973,340 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits 46 1997
* 6,160,276 Double-sided programmable interconnect structure 14 1999
* 2001/0009,032 Structure having multiple levels of programmable integrated circuits for interconnecting electronic components 7 2001
 
MENTOR GRAPHICS (HOLDING) LTD. (3)
* 5,777,489 Field programmable gate array with integrated debugging facilities 65 1995
* 5,907,697 Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network 21 1996
6,717,433 Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect 8 2002
 
BANK OF AMERICA, N.A. (7)
* 5,614,756 Metal-to-metal antifuse with conductive 62 1994
* 5,744,980 Flexible, high-performance static RAM architecture for field-programmable gate arrays 146 1996
* 5,936,426 Logic function module for field programmable array 8 1997
7,382,156 Method and apparatus for universal program controlled bus architecture 43 2005
7,409,664 Architecture and interconnect scheme for programmable logic circuits 2 2005
7,646,218 Architecture and interconnect scheme for programmable logic circuits 1 2008
7,915,918 Method and apparatus for universal program controlled bus architecture 0 2010
 
OTRSOTECH, LLC (3)
* 6,014,038 Function block architecture for gate array 30 1997
6,223,313 Method and apparatus for controlling and observing data in a logic block-based asic 20 1997
6,611,932 Method and apparatus for controlling and observing data in a logic block-based ASIC 11 2002
 
Prolinx Labs Corporation (14)
* 5,813,881 Programmable cable and cable adapter using fuses and antifuses 16 1994
* 5,808,351 Programmable/reprogramable structure using fuses and antifuses 50 1994
* 5,726,482 Device-under-test card for a burn-in board 13 1994
* 5,572,409 Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board 46 1994
* 5,537,108 Method and structure for programming fuses 44 1994
* 5,962,815 Antifuse interconnect between two conducting layers of a printed circuit board 38 1995
* 5,834,824 Use of conductive particles in a nonconductive body as an integrated circuit antifuse 50 1995
* 5,906,042 Method and structure to interconnect traces of two conductive layers in a printed circuit board 91 1995
* 5,767,575 Ball grid array structure and method for packaging an integrated circuit chip 58 1995
* 5,872,338 Multilayer board having insulating isolation rings 65 1996
* 5,917,229 Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect 29 1996
* 5,906,043 Programmable/reprogrammable structure using fuses and antifuses 4 1997
* 5,987,744 Method for supporting one or more electronic components 25 1997
* 6,034,427 Ball grid array structure and method for packaging an integrated circuit chip 169 1998
 
QuickLogic Corporation (25)
* 5,122,685 Programmable application specific integrated circuit and logic cell therefor 302 1991
* 5,220,213 Programmable application specific integrated circuit and logic cell therefor 123 1992
* 5,294,846 Method and apparatus for programming anti-fuse devices 32 1992
* 5,280,202 Programmable application specific integrated circuit and logic cell therefor 104 1993
* 5,502,315 Electrically programmable interconnect structure having a PECVD amorphous silicon element 50 1993
* 5,416,367 Programmable application specific integrated circuit and logic cell therefor 33 1994
* 5,396,127 Programmable application specific integrated circuit and logic cell therefor 23 1994
* 5,430,390 Programmable application specific integrated circuit and logic cell therefor 19 1994
* 5,424,655 Programmable application specific integrated circuit employing antifuses and methods therefor 45 1994
* 5,717,230 Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses 10 1994
* 5,552,720 Method for simultaneous programming of multiple antifuses 8 1994
* 5,495,181 Integrated circuit facilitating simultaneous programming of multiple antifuses 58 1994
* 5,477,167 Programmable application specific integrated circuit using logic circuits to program antifuses therein 31 1995
* 5,469,109 Method and apparatus for programming anti-fuse devices 15 1995
* 5,587,669 Programmable application specific integrated circuit and logic cell therefor 13 1995
* 5,594,364 Programmable application specific integrated circuit and logic cell therefor 19 1995
* 5,654,649 Programmable application specific integrated circuit employing antifuses and methods therefor 22 1995
* 5,600,262 Integrated circuit facilitating simultaneous programming of multiple antifuses 74 1995
* 5,780,919 Electrically programmable interconnect structure having a PECVD amorphous silicon element 24 1996
* 5,682,106 Logic module for field programmable gate array 17 1996
* 5,726,586 Programmable application specific integrated circuit and logic cell therefor 5 1996
* 5,892,684 Programmable application specific integrated circuit employing antifuses and methods therefor 5 1997
* 5,986,468 Programmable application specific integrated circuit and logic cell therefor 11 1997
* 6,078,191 Programmable application specific integrated circuit and logic cell 33 1998
* 6,150,199 Method for fabrication of programmable interconnect structure 9 1999
 
LIGHTSPEED SEMICONDUCTOR (1)
6,696,856 Function block architecture with variable drive strengths 12 2001
 
LATTICE SEMICONDUCTOR CORPORATION (8)
* 5,260,881 Programmable gate array with improved configurable logic block 73 1989
* 5,128,871 Apparatus and method for allocation of resoures in programmable logic devices 208 1990
* 5,185,706 Programmable gate array with logic cells having configurable output enable 70 1990
* 5,255,203 Interconnect structure for programmable logic device 81 1990
* 5,359,536 Programmable gate array with improved interconnect structure, input/output structure and configurable logic block 40 1993
* 5,381,058 FPGA having PFU with programmable output driver inputs 48 1993
* 5,644,496 Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses 53 1993
* 5,740,069 Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs) 41 1996
 
PACT XPP TECHNOLOGIES AG (3)
9,037,807 Processor arrangement on a chip including data processing, memory, and interface elements 0 2010
9,075,605 Methods and devices for treating and processing data 0 2012
9,092,595 Multiprocessor having associated RAM units 0 2014
 
UNIVERSITY OF WASHINGTON (1)
* 5,208,491 Field programmable gate array 407 1992
 
FEI COMPANY (1)
* 5,166,556 Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits 175 1991
 
Crosspoint Solutions, Inc. (10)
* 5,221,865 Programmable input/output buffer circuit with test capability 102 1991
* 5,313,119 Field programmable gate array 85 1991
* 5,347,519 Preprogramming testing in a field programmable gate array 89 1991
* 5,384,481 Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof 21 1993
* 5,527,745 Method of fabricating antifuses in an integrated circuit device and resulting structure 16 1993
* 5,394,103 Field programmable gate array 6 1994
* 5,623,501 Preprogramming testing in a field programmable gate array 21 1994
* 5,493,147 Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof 18 1994
* 5,465,055 RAM-logic tile for field programmable gate arrays 9 1994
* 5,629,636 Ram-logic tile for field programmable gate arrays 4 1995
 
VIRTUAL COMPUTER CORPORATION (1)
* 5,684,980 FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions 190 1996
 
HITACHI VLSI ENGINEERING CORPORATION (1)
* 4,982,114 Semiconductor logic device having two-dimensional logic arrays and logic cell chains alternately arranged 9 1989
 
IOWA STATE UNIVERSITY RESEARCH FOUNDATION, INC. (2)
8,661,394 Depth-optimal mapping of logic chains in reconfigurable fabrics 0 2008
8,438,522 Logic element architecture for generic logic chains in programmable devices 0 2008
 
Versity Design, Inc. (2)
* 6,009,256 Simulation/emulation system and method 116 1997
6,321,366 Timing-insensitive glitch-free logic system and method 131 1998
 
KAWASAKI MICROELECTRONICS, INC. (3)
* 5,003,200 Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a single switch station 51 1989
* 4,963,770 Programmable logic device 92 1990
* 5,153,463 Programmable logic device having a reduced switching matrix 10 1991
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
* 5,633,806 Semiconductor integrated circuit and method of designing same 11 1995
 
OVONYX, INC. (1)
* 7,646,630 Programmable matrix array with chalcogenide material 12 2005
 
ATMEL CORPORATION (5)
* 5,089,973 Programmable logic cell and array 41 1989
* 5,019,736 Programmable logic cell and array 81 1989
* 5,144,166 Programmable logic cell and array 356 1990
* 5,245,227 Versatile programmable logic cell for use in configurable logic arrays 134 1991
* 5,218,240 Programmable logic cell and array with bus repeaters 95 1992
* Cited By Examiner