Importance

Loading Importance Indicators...

Abstract

An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.

Loading the Abstract Image...

First Claim