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Abstract

A direct memory access (DMA) system with a single bus architecture for controlling data transfers and storage between plural digital processors and plural Input/Output devices. Limiters are included for disabling access to the bus of a processor whose access time exceeds a predetermined time interval. A time governor is included to suppress processor access to the bus when total processor access time in a data communication cycle has exceeded a predetermined time interval. The input and output devices are coupled to the bus through interface isolation circuits that prevent faults in the input and output devices from propagating to the system to cause total system failure. An input or output device fault can only result in erroneous data being provided to a location of the DMA memory reserved for the faulted device. The DMA memory is protected by a Write-Protect Decoding Circuit that prevents processor writing into prohibited areas of the memory.

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First Claim