Process for formation of shallow silicided junctions
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United States of America Patent
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-
Nov 29, 1988
Grant Date -
N/A
app pub date -
Mar 31, 1987
filing date -
Mar 31, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.
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