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Abstract

A synchronous timer anti-alias filter gain stage utilizing switched capacitor circuitry is described. A high frequency sampling clock is used for a switched capacitor anti-alias filter. In the preferred embodiment, a clock of approximately 921.6 kilohertz is utilized. This fast clock is divided down by a programmable timer into a low frequency sampling clock to drive a signal gain stage. The programmable divide values are integers so that the anti-alias filter clock and gain stage clock are in an integer relationship with each other for edge locking. The high frequency clock is divided down by a fixed divider to provide a clocking signal to an input band pass filter. The fixed divide value is also an integer so that the band pass filter clock and anti-alias filter clock are in integer relationship with each other. Switched capacitor anti-alias filters are used in place of continuous time, R-C anti-alias filters. The switched capacitor anti-alias filter has greater accuracy than R-C filters, approaching the range of 0.2% accuracy of the time constant. In addition, the switched caapcitor anti-alias filter requires less silicon area than equivalent R-C filters in integrated cirucit implementations. DC offsets are eliminated by preceding and following the gain stage by first order high pass filters. The programmability of the low frequency sampling clock rate, by changing the divide values, allows the received baud rate to be tracked in modem applications.

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First Claim