Logic gate system design

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United States of America Patent

PATENT NO 4791578
SERIAL NO

06947612

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Abstract

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A method for evaluating the testability of circuit systems containing a plurality of logic gates through evaluating statistical properties in response to selected inputs.

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Patent Owner(s)

Patent OwnerAddress
CONTROL DATA CORPORATION8100-34TH AVENUE SOUTH A CORP OF DE MINNEAPOLIS MN 55440

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fazio, Dennis Minneapolis, MN 1 19
Harris, Thomas J Shoreview, MN 30 1410

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