Importance

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Abstract

Column circuitry for a CMOS static RAM includes a bit line clamp combined with a bit line current source regulated by a voltage reference which tracks changes in transistor characteristics. Separate data read and data write lines are provided, with a differential amplifier for each pair of bit lines. The data read lines are coupled to compensated current source loads, and the differential amplifiers are coupled to switching transistors which are also compensated for transistor characteristic changes. Each bit line pair has a sneak capacitance prevention transistor so that in non-selected columns the bit line pairs are coupled together allowing the memory cells therein to pull down all of the bit lines. This isolates the read lines from unwanted capacitance in the differential amplifiers of each of the non-selected columns. Further, a VCC protection circuit is provided.

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First Claim