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Abstract

A high speed memory system for 100% bandwidth use with a control bus bearing contiguous sequentially intermixed data read and data write signals including a first buffer for reading data from a storage means into the data bus and a second buffer for writing data from the data bus into the storage means and a memory control sensitive to the order of received write requests and read requests signals to avoid any simultaneous utilization of the data bus and storage means in accordance with a prearranged schedule of preferential utilization of the data bus and storage means. The subject invention and related method further contemplates the employment of a plurality of input/output ports which are responsive to data read and/or data write request signals on the control bus for reading data from and/or writing data into the data bus in synchronism with the utilization of the first and second buffers.

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First Claim