Importance

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Abstract

A data processing system includes a plurality of memory access devices, each having a characteristic operating speed, for writing data into and reading data from a dynamic random access memory (DRAM) as well as a memory controller for accessing a plurality of addressable storage locations in the DRAM for either storing data in or reading stored data from the various storage locations in the DRAM. The system further includes a dynamic column address strobe (CAS) signal generator responsive to a memory access cycle signal, or READ pulse, and a conventional CAS signal for generating a dynamic CAS signal having a floating trailing edge which extends to the end of the memory access cycle as well as to the trailing edge of the READ pulse irrespective of the length of the memory access cycle signal to allow data to be read from the DRAM by any memory access device regardless of its operating speed during a memory access signal without losing or temporarily storing this data prior to providing it to the memory access device.

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First Claim