Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
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United States of America Patent
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Dec 27, 1988
Grant Date -
N/A
app pub date -
Jul 3, 1984
filing date -
Jul 3, 1984
priority date (Note) -
Expired
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Abstract
A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors.
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