Layout for stable high speed semiconductor memory device
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United States of America Patent
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Jan 3, 1989
Grant Date -
N/A
app pub date -
Feb 17, 1987
filing date -
Feb 18, 1986
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.
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