Dual port memory controller
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United States of America Patent
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-
Jan 3, 1989
Grant Date -
N/A
app pub date -
Oct 20, 1987
filing date -
Oct 20, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A dual port memory controller is operative to interface a pair of processors to a common multiple bank organized memory. A dedicated logic array provides arbitration between conflicting processor requests for memory access. Refresh means are operative upon the memory banks in a staggered fashion to minimize noise created within the system during refresh and to permit simultaneous refresh of an access to the memory.
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