Interleaved synchronous bus access protocol for a shared memory multi-processor system
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United States of America Patent
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Jan 10, 1989
Grant Date -
N/A
app pub date -
Nov 22, 1985
filing date -
Nov 22, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for sharing several memory modules by several processors on a common bus uses a protocol in which, after a processor gains access to a memory module read or write data is transferred on the bus within a preset number of system clock periods. After priority is established by polling, the processor sends memory address on the common bus. For each operation several idle system clock periods are provided before data is returned from the memory to permit the memory to retrieve the data. Meanwhile, the protocol interleaves requests for access to other memory modules from other processors thereby increasing the throughput of the system.
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