Bus master having burst transfer mode
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United States of America Patent
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-
Jan 17, 1989
Grant Date -
N/A
app pub date -
Sep 18, 1986
filing date -
Sep 18, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.
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