Sample hold circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 31, 1989
Grant Date -
N/A
app pub date -
Sep 2, 1987
filing date -
Sep 10, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A sample hold circuit consists of a variable gain voltage-to-current converter and an integration circuit which are connected in series. The conversion gain of the variable gain voltage-to-current converter varies in response to a level of a sampling pulse and one of a follow mode and a hold mode is selected in response to the level of the sampling pulse. In the follow mode when the level of the sampling pulse is high, the conversion gain of the converter is set to the maximum and an output signal of the integration circuit follows up an analog input signal which is inputted into the converter. In the hold mode when the level of the sampling pulse is low, the conversion gain of the converter is set to the minimum and the level of the output signal of the integration circuit is held at a level just before the hold mode is selected.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully