Method of fabrication of semiconductor device having a planar configuration
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United States of America Patent
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Feb 7, 1989
Grant Date -
N/A
app pub date -
Jun 29, 1987
filing date -
Jun 29, 1987
priority date (Note) -
Expired
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Abstract
An MOS device having a planar configuration in which the top surfaces of the source, drain and gate electrodes are coplanar, and the overlying electrical contact structure is also planar, is produced by a method of fabrication in which the gate is defined by forming an oxide mesa on a substrate, building up the substrate with semiconductor material around the mesa, removing the mesa, and filling the resultant trough with doped polysilicon to form the self-aligned gate. Line width and alignment control are enchanced. The planarity of the device and the improved dimensional control enable a reduction of device dimensions and consequently increased device density in integrated circuits.
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