Method for limiting chippage when sawing a semiconductor wafer
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United States of America Patent
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Feb 14, 1989
Grant Date -
N/A
app pub date -
Sep 11, 1986
filing date -
Sep 30, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for limiting chippage when sawing a semiconductor wafer into individual pieces which involves providing a dielectric layer at least in some portions of the wafer surface. A border of the dielectric layer is applied to the margins of the individual parts which are to be formed on the surface of the semiconductor wafer, being applied under such conditions that the margins exert a tensile stress on the semiconductor surface. This produces a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material in the sawing region on the surface of the semiconductor wafer.
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