A massively parallel processor comprising 65,534 (=2.sup.16) individual processors is organized so that there are 16 (=2.sup.4) individual processors on each of 4,096 (=2.sup.12) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=2.sup.5) integrated circuits and each backplane carries 16 (=2.sup.4) circuit boards. There are eight (=2.sup.3) backplanes advantageously arranged in a cube that is 2.times.2.times.2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane. Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane. As a result of this arrangement, all message packets are first routed to nearest neighbor ICs located on the same circuit board; all message packets are then routed to nearest neighbor ICs located on the same backplane; and finally, all message packets are then routed to nearest neighbor ICs located on different backplanes.
* 5193202 Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
* 5157785 Process cell for an N-dimensional processor array having a single input element with 2N data inputs, memory, and full function arithmetic logic unit
* 5133073 Processor array of N-dimensions which is physically reconfigurable into N-1
* 5442797 Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
* 5613136 Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor
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