Method and apparatus for interconnecting processors in a hyper-dimensional array

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4805091
SERIAL NO

06740943

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Abstract

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A massively parallel processor comprising 65,534 (=2.sup.16) individual processors is organized so that there are 16 (=2.sup.4) individual processors on each of 4,096 (=2.sup.12) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=2.sup.5) integrated circuits and each backplane carries 16 (=2.sup.4) circuit boards. There are eight (=2.sup.3) backplanes advantageously arranged in a cube that is 2.times.2.times.2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane. Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane. As a result of this arrangement, all message packets are first routed to nearest neighbor ICs located on the same circuit board; all message packets are then routed to nearest neighbor ICs located on the same backplane; and finally, all message packets are then routed to nearest neighbor ICs located on different backplanes.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Thinking Machines CorporationWILMINGTON, DE18
TM PATENTS, L.P.WILMINGTON, DE21

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Clayton, Richard Stow, MA 5 108
Feyman, Carl Cambridge, MA 1 105
Hillis, W D Cambridge, MA 1 105
Kahle, Brewster Boston, MA 12 1071
Thiel, Tamiko Somerville, MA 1 105

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