Active load for emitter coupled logic gate
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United States of America Patent
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-
Feb 21, 1989
Grant Date -
N/A
app pub date -
Mar 28, 1988
filing date -
Mar 28, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.
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