Circuit and method for performing equal duty cycle odd value clock division and clock synchronization

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4807266
SERIAL NO

07101946

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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A circuit for dividing a master clock by an odd integral value and producing a 50% duty cycle. A state machine develops set and clear signals which are of a timing proportion of n: n+1, where 2n+1 is the divisor value. The set signal is provided to one input of a bistable multivibrator or S-R latch to set the multivibrator to a given state, while the clear signal is combined with the master clock signal to delay or disable the clearing of the multivibrator by 1/2 count of the master clock, so that an n+1/2: n+1/2 proportion output clock signal is developed. Additionally, the circuit includes a state machine which determines which of a series of differing frequency master clock signals is active and when an external triggering event occurs so that the following rising edge of the output clock signal is delayed until a determined time after the triggering event to allow synchronization of the output clock signal.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.HOUSTON, TX13355

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Taylor, Mark Houston, TX 75 1105

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ADVANCED MICRO DEVICES, INC. (1)
* 4703495 High speed frequency divide-by-5 circuit 11 1986
 
NEC CORPORATION (1)
* 4656649 Clock frequency divider circuit 30 1985
 
SOCIETE DE RECHERCHES ET DE SNYTHESES ORGAIQUES SA (1)
* 4336394 Cyano-ureas, cyano-thioureas and their preparation methods 1 1980
 
Sperry Corporation (1)
* 4560939 Synchronized selectable rate clocking system 16 1984
 
AVAYA TECHNOLOGY CORP. (1)
* 4651103 Phase adjustment system 23 1985
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
QUALCOMM INCORPORATED (1)
6389095 Divide-by-three circuit 11 2000
 
WI-LAN INC. (1)
* 4891825 Fully synchronized programmable counter with a near 50% duty cycle output signal 23 1988
 
TM PATENTS, L.P. (1)
* 5118975 Digital clock buffer circuit providing controllable delay 114 1990
 
NXP B.V. (1)
* 5250858 Double-edge triggered memory device and system 21 1992
 
CISCO TECHNOLOGY, INC. (1)
* 5577238 Multistage timing circuit having multiple counters in each timer for generating programmable duration output signals without any delay 3 1996
 
INTEL CORPORATION (4)
* 5317202 Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle 100 1992
* 5410263 Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle 107 1993
* 5914996 Multiple clock frequency divider with fifty percent duty cycle output 125 1997
* 6185691 Clock generation 11 1997
 
INPHI CORPORATION (1)
* 2008/0219,399 Frequency Divider With Symmetrical Output 3 2007
 
NXP USA, INC. (1)
7898353 Clock conditioning circuit 0 2009
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
* 6033441 Method and apparatus for synchronizing data transfer 28 1997
 
TELASIC COMMUNICATIONS (1)
* 4975931 High speed programmable divider 22 1988
 
ORACLE AMERICA, INC. (2)
* 6882196 Duty cycle corrector 16 2002
* 2004/0012,428 Duty cycle corrector 1 2002
* Cited By Examiner