US Patent No: 4,807,266

Number of patents in Portfolio can not be more than 2000

Circuit and method for performing equal duty cycle odd value clock division and clock synchronization

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A circuit for dividing a master clock by an odd integral value and producing a 50% duty cycle. A state machine develops set and clear signals which are of a timing proportion of n: n+1, where 2n+1 is the divisor value. The set signal is provided to one input of a bistable multivibrator or S-R latch to set the multivibrator to a given state, while the clear signal is combined with the master clock signal to delay or disable the clearing of the multivibrator by 1/2 count of the master clock, so that an n+1/2: n+1/2 proportion output clock signal is developed. Additionally, the circuit includes a state machine which determines which of a series of differing frequency master clock signals is active and when an external triggering event occurs so that the following rising edge of the output clock signal is delayed until a determined time after the triggering event to allow synchronization of the output clock signal.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.HOUSTON, TX23149

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Taylor, Mark Dalby, AU 83 757

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ADVANCED MICRO DEVICES, INC. (1)
* 4,703,495 High speed frequency divide-by-5 circuit 11 1986
 
AVAYA TECHNOLOGY CORP. (1)
* 4,651,103 Phase adjustment system 23 1985
 
NEC CORPORATION (1)
* 4,656,649 Clock frequency divider circuit 29 1985
 
SOCIETE DE RECHERCHES ET DE SNYTHESES ORGAIQUES SA (1)
* 4,336,394 Cyano-ureas, cyano-thioureas and their preparation methods 1 1980
 
Sperry Corporation (1)
* 4,560,939 Synchronized selectable rate clocking system 16 1984
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTEL CORPORATION (4)
* 5,317,202 Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle 95 1992
* 5,410,263 Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle 105 1993
* 5,914,996 Multiple clock frequency divider with fifty percent duty cycle output 64 1997
* 6,185,691 Clock generation 11 1997
 
CISCO TECHNOLOGY, INC. (1)
* 5,577,238 Multistage timing circuit having multiple counters in each timer for generating programmable duration output signals without any delay 3 1996
 
FREESCALE SEMICONDUCTOR, INC. (1)
7,898,353 Clock conditioning circuit 0 2009
 
LSI CORPORATION (1)
* 6,033,441 Method and apparatus for synchronizing data transfer 26 1997
 
NXP B.V. (1)
* 5,250,858 Double-edge triggered memory device and system 19 1992
 
QUALCOMM INCORPORATED (1)
6,389,095 Divide-by-three circuit 10 2000
 
SUN MICROSYSTEMS, INC. (1)
* 6,882,196 Duty cycle corrector 15 2002
 
TELASIC COMMUNICATIONS (1)
* 4,975,931 High speed programmable divider 21 1988
 
TM PATENTS, L.P. (1)
* 5,118,975 Digital clock buffer circuit providing controllable delay 113 1990
 
WI-LAN INC. (1)
* 4,891,825 Fully synchronized programmable counter with a near 50% duty cycle output signal 23 1988
* Cited By Examiner