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Abstract

A data assembler and serializer for use in bit mapped graphics systems where flexible windowing and panning are desired. The unit accepts display memory data as either one 8-bit word or two 4-bit words. Leading and trailing pixels not required in the final bit stream, as indicated by control data, are removed from the words. Remaining pixels are then shifted and concatenated to form a continuous stream of video data. The assembled data words are supplied to a FIFO buffer and from the buffer to a shift register for generating a serial output. Positioned between a display memory and a color palette or monitor, the system supports smooth panning and hardware windows on pixel boundaries.

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First Claim