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Abstract

A coprocessor architecture specifically adapted for parallel operation as one of an array of coprocessors is described. Each of the coprocessors of the array are commonly responsive to a host processor. The coprocessor architecture preferably includes a selector for enabling the responsiveness of the coprocessor architecture to instructions from the host processor including an enabled responsiveness unique among the plurality of coprocessors and enabled responsiveness that is in common with that of the plurality of the coprocessors. The coprocessor architecture further includes a microengine for qualifying the responsiveness of the coprocessor to instructions provided by the host processor including qualification of the enabled responsiveness of the coprocessor architecture as provided for by the selector. Consequently, the coprocessors of the array are readily managed both individually and, from the perspective of the host processor, as a single entity operating as a single instruction, multiple data machine. As such, the coprocessor array requires little, if any, managerial support from the host processor, regardless of the specific number of coprocessors participating in the coprocessor array.

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First Claim