US Patent No: 4,810,667

Number of patents in Portfolio can not be more than 2000

Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer

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Abstract

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The disclosure relates to a method of forming an isolated semiconductor, preferably of the vertical bipolar variety, wherein a porous highly doped semiconductor layer is oxidized and, with a trench containing silicon oxide therein, forms a region encasing a moderately doped epitaxial layer disposed beneath a lightly doped epitaxial layer. The vertical bipolar device is formed in the moderately doped and lightly doped layers with the highly doped epitaxially deposited layer, which is now a silicon oxide layer, forming a portion of the isolation. The anodization of the highly doped layer takes place using an anodizing acid at a temperature of from about 0 to about 10 degrees C.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
TEXAS INSTRUMENTS INCORPORATEDDALLAS, TX18119

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Spratt, David B Plano, TX 18 294
Yeakley, Richard L Dallas, TX 4 88
Zorinsky, Eldon J Plano, TX 11 201

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Bell Telephone Laboratories, Incorporated (1)
4,643,804 Forming thick dielectric at the bottoms of trenches utilized in integrated-circuit devices 9 1985
 
TEXAS INSTRUMENTS INCORPORATED (1)
4,628,591 Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon 27 1984

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (3)
6,489,192 Base current reversal SRAM memory cell and method 2 2001
6,699,742 Base current reversal SRAM memory cell and method 0 2002
6,891,213 Base current reversal SRAM memory cell and method 1 2003
 
NATIONAL SEMICONDUCTOR CORPORATION (3)
5,043,292 Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures 7 1990
5,372,952 Method for forming isolated semiconductor structures 9 1992
5,376,560 Method for forming isolated semiconductor structures 64 1994
 
CYPRESS SEMICONDUCTOR CORPORATION (2)
5,897,354 Method of forming a non-volatile memory device with ramped tunnel dielectric layer 48 1996
5,741,737 MOS transistor with ramped gate oxide thickness and method for making same 32 1996
 
TEXAS INSTRUMENTS INCORPORATED (2)
4,982,263 Anodizable strain layer for SOI semiconductor structures 15 1989
5,049,513 Bi CMOS/SOI process flow 10 1990
 
YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM (2)
8,828,781 Method for producing photovoltaic device isolated by porous silicon 0 2013
8,829,332 Photovoltaic device formed on porous silicon isolation 0 2013
 
AEROFLEX COLORADO SPRINGS INC. (1)
5,561,073 Method of fabricating an isolation trench for analog bipolar devices in harsh environments 24 1994
 
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE (1)
5,773,353 Method of fabricating a semiconductor substrate 2 1995
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,217,920 Method of forming substrate contact trenches and isolation trenches using anodization for isolation 27 1992
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,306,659 Reach-through isolation etching method for silicon-on-insulator devices 12 1993
 
KABUSHIKI KAISHA TOSHIBA (1)
5,688,702 Process of making a semiconductor device using a silicon-on-insulator substrate 17 1994
 
MAGNACHIP SEMICONDUCTOR, LTD. (1)
5,686,342 Method for insulating semiconductor elements 9 1995
 
MICROSEMI CORPORATION (1)
5,049,521 Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate 26 1989
 
NEC ELECTRONICS CORPORATION (1)
5,494,846 Method of manufacturing semiconductor device 25 1994
 
SGS-THOMSON MICROELECTRONICS, INC. (1)
5,135,884 Method of producing isoplanar isolated active regions 3 1991
 
STMICROELECTRONICS S.A. (1)
7,456,071 Method for forming a strongly-conductive buried layer in a semiconductor substrate 1 2005
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
4,910,165 Method for forming epitaxial silicon on insulator structures using oxidized porous silicon 24 1988
 
The United States of America as represented by the Secretary of the Navy (1)
5,420,049 Method of controlling photoemission from porous silicon using ion implantation 11 1993
 
UTMC MICROELECTRONIC SYSTEMS INC. (1)
5,344,785 Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate 29 1993
 
Westinghouse Electric Corp. (1)
5,110,755 Process for forming a component insulator on a silicon substrate 8 1990
 
Other [Check patent profile for assignment information] (2)
4,927,781 Method of making a silicon integrated circuit waveguide 15 1989
5,057,022 Method of making a silicon integrated circuit waveguide 11 1990