High speed logic circuit having feedback to prevent current in the output stage
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United States of America Patent
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-
Mar 7, 1989
Issued Date -
N/A
app pub date -
Apr 11, 1988
filing date -
Jun 23, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved FET capacitance driver logic circuit having an inverter feedback stage 22 connected from output to input of output FET 23 to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.
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Cited Art Landscape
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