Importance

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Abstract

A computer is sped up by reducing significantly the time necessary for the computer to detect and respond to an overflow following an ALU operation of a type which generates an overflow. This is done by assuring the next instruction in sequence is the one to be executed and in parallel detecting the occurrence of an overflow as the result of an implementation of a selected instruction and then producing a flag in response to the overflow. The flag is detected, and selected portions of the computer are disabled to inhibit any change in state within the computer following the generation of the overflow. An interrrupt sequence is then implemented to correct the output of the instruction which generated the overflow to compensate for the overflow. The next following instruction is then implemented after completion of the interrupt routine. Consequently, a delay following each instruction of a type which can generate an overflow is avoided unless an overflow condition actually exists because should an overflow not exist the computer automatically implements the next correct following instruction. In an alternative embodiment, an ALU operation capable of producing a branch signal is followed by the most likely microinstruction to occur. Should, however, the ALU operation indicate a branch, selected components of the computer are disabled to inhibit any change in state within the computer following the generation of the branch signal. An alternative microinstruction is then implemented in response to the branch signal. A selected sequence of microinstructions is then implemented following the completion of the alternative microinstruction. Consequently, a delay following each instruction of a type which can generate a branch is avoided unless a branch signal actually is generated.

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First Claim