Address transformation circuit arrangement
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United States of America Patent
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-
Mar 7, 1989
Grant Date -
N/A
app pub date -
Oct 3, 1986
filing date -
Oct 18, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Two circuit arrangements are described for transforming 2.sup.n global addresses used in a control engineering system having several local units into 2.sup.m local addresses used in one of the units of the system. One of these contains several memories in which subfunctions resulting from a splitting of the transformation function conveying the transformation are stored. The other circuit arrangement contains a single memory which accepts all subfunctions. The transformation function is split into the subfunctions in such a manner that an optimum compromise is achieved between the storage space required for storing the subfunctions and the time required for the transformation.
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