Boundary-free semiconductor memory device

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United States of America Patent

PATENT NO 4811297
SERIAL NO

07132442

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Abstract

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An entire chip is divided into N blocks (N=n.times.m) in accordance with a desired rectangular group of bits (n.times.m bits). The same row decoder is provided for every m blocks, and a row address A.sub.R or a row address A.sub.R+1 adjacent thereto is given to the row decoders. Similarly, the same column decoder is provided for every m blocks, and a column address A.sub.C or a column address A.sub.C +1 adjacent thereto is given to the column decoders. N bits of memory cells are accessed from the blocks, and the accessed memory cells are rearranged, thereby obtaining a desired rectangular group of bits.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITEDKAWASAKI-SHI KANAGAWA 211-8588

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ogawa, Junji Yokohama, JP 140 2961

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