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Abstract

A Dynamic Memory Access (DMA) control device for transmitting data between a data transmitter and a data receiver via an external bus formed of a data bus, an address bus and a control bus, and has a multiplicity of data transmitters/receivers and at least one microprocessor connected thereto. The transmission of the data in the external bus depends upon a channel program containing channel transfer commands and channel control commands, and includes a central control unit for addressing, dependent upon a channel command, a microcommand, address and control signals corresponding to the microcommand on an internal address-control bus; an address unit is connected to the internal address/control bus and to an internal data bus wherein addresses of a data transmitter, data receiver and the channel program are stored. The address unit delivers an address and simultaneously computes and stores the delivered address; a data unit provides interim data storage; a byte counter unit is connected to the internal data bus and address/control bus for counting the number of bytes to be transmitted; a data transmitting bus interface circuit is connected to the output of the address unit, to the external address bus and to the internal address/control bus, and to the external data bus. A control register is connected to the internal bus for receiving a channel command word, status words and other control information, from which lines for transmitting control signals extend to the central control unit; the units have devices for independently executing the tasks assigned to them.

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First Claim