Importance

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Abstract

Multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits. The first stage buffer circuits are arranged in the neighborhood of the input pins, and the second stage buffer circuits are arranged on the central portion of the chip. Equivalent-length wirings are made between the successive two stage buffer circuits and the same number of subsequent stage buffer circuit are connected with each of certain stage buffer circuits for the respective phases so as to provide equal resistances and equal capacitances. Equivalent-length wirings are also made between final stage buffer circuits and the corresponding load circuits, and the same number of load circuits are connected with each final stage buffer circuit. Thus, equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.

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First Claim