A plurality of operation units are connected to one another. The operation units include a processor, a buffer memory, and a data transfer control circuit connected between the processor and the buffer memory for controlling the data input-output with the buffer memories in the other of the operation units. The buffer memories and the data transfer control circuit are connected with one another by data buses, respectively.
* 5,361,370 Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port
* 5,530,884 System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data
* 5,517,665 System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission
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