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United States of America Patent

PATENT NO 4817025
SERIAL NO

07154466

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Abstract

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A digital filter of linear phase non-cyclic type comprises a shift register composed of serially connected delay elements with a specified delay time. The outputs from the individual delay elements are multiplied and added so that the output sampling frequency is twice that of the input sampling frequency which enters the shift register. The number of multiplications is significantly reduced by making the number of output lines from the delay elements to be odd and by placing adders between the shift register and the device for carrying out multiplications. An alternative method is to use read only memories instead of the means for carrying out multiplications.

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Patent Owner(s)

Patent OwnerAddress
SHARP KABUSHIKI KAISHAOSAKA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Asai, Shin Tenri, JP 5 33
Miyakoshi, Kazumitsu Yamatokoriyama, JP 4 49
Mochisuki, Daisuke Nara, JP 1 19

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