Processing circuit capable of raising throughput of accumulation
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United States of America Patent
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-
Mar 28, 1989
Grant Date -
N/A
app pub date -
Jul 9, 1986
filing date -
Jul 9, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital signal processing circuit reduces the occurrence of overflow conditions during successive arithmetic operations. The product output of a multiplication circuit is shifted by a barrel shifter to round off a predetermined number of least significant bits, thereby reducing the occurrence of an overflow condition when the successive product outputs of the multiplication circuit are summed by an arithmetic logic unit (ALU) to produce a summed output. The summed output is then shifted toward the most significant bit by a predetermined number before an output signal is generated. An overflow detection and correction circuit is provided in the event of an overflow condition occurring either to the ALU or the barrel shifter.
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