Importance

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Abstract

A system for providing concurrent access to an addressable memory space by a plurality of data processing devices includes a plurality of independently accessible memory banks, each memory bank providing a separate portion of the addressable memory space. A memory management unit includes address and data multiplexers corresponding to each memory bank for providing access by any selected one of the data processing devices to the corresponding memory bank and also includes circuits for controlling the multiplexers to permit different processing devices to access different memory banks at the same time while arbitrating competing demands for the same memory bank.

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First Claim