Wired "OR" bus evaluator for logic simulation
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United States of America Patent
Stats
-
Apr 11, 1989
Issued Date -
N/A
app pub date -
Mar 7, 1988
filing date -
Jun 30, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention consists of a hardware simulator with bus evaluator logic for use in simulating and fault grading of very large scale digital circuits containing buses. In this invention the status of a bus is continously upgraded each time a primitive is evaluated that has an output coupled to the bus. As bus driver primitives are evaluated, the state of the bus is determined on the fly and stored in an accumulator register, called the bus register. Evaluation of the bus continues using the data stored in the bus register and the state of each driver until all drivers have been evaluated. After the last bus driver is evaluated the state of the bus is known and the bus primitive is assigned the value, or state, stored in the bus register hardware and is passed to all receivers on the bus.
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