Method and apparatus for selectively evaluating an effective address for a coprocessor
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United States of America Patent
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Apr 11, 1989
Issued Date -
N/A
app pub date -
Dec 21, 1987
filing date -
Apr 18, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word, Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives whcih define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
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