Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
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United States of America Patent
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Apr 18, 1989
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N/A
app pub date -
Aug 27, 1987
filing date -
Aug 27, 1987
priority date (Note) -
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Abstract
A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.
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