MOS no-leak circuit
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United States of America Patent
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-
Apr 25, 1989
Grant Date -
N/A
app pub date -
Apr 8, 1987
filing date -
Apr 8, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A CMOS inverter circuit is coupled to a power source by a cut-off circuit which prevents current flow through the CMOS inverter circuit when the input signal to the CMOS inverter is of a first bi-level state. The cut-off circuit responds to the output signal from a second inverter circuit that is connected to receive the output of the CMOS inverter circuit. A second embodiment of the invention provides a latching function by connecting a feedback path from the output of the second inverter circuit to a toggle gate circuit connected to the input to said CMOS inverter circuit.
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