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Abstract

A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a multiplicand and performing the multiplication of the multiplicand and the multiplier on the basis of Booth's algorithm; and an adder for obtaining the final products on the basis of the outputs from the cell array blocks. In order to enable the functionally divisional operation, the cell array blocks includes complex cells which operate as the basic cells in the non-division mode and which operate as the code cells in the division mode. Further, the cell array blocks include selectors to supply an inactive value to the cells to perform the multiplication of the upper bits of the multiplicand and the lower bits of the multiplier and to the cells to perform the multiplication of the lower bits of the multiplicand and the upper bits of the multiplier in such a manner that the cell array blocks can supply the multiplicand and its inverted data to the cells constituting the cell array blocks in the non-division mode and can simultaneously execute two series of multiplications in the division mode.

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First Claim