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Abstract

A phase-locked loop compares the loop output clock with the loop input clock in a digital phase detector to provide lead/lag error signal samples. A microprocessor utilizes the lead/lag error samples to track the input clock in a wideband mode matching the bandwidth of the input and in a very narrow band mode. When the system in which the loop is utilized switches to a new input clock source, the microprocessor resets the loop divider chain so that the loop feedback signal is phase coincident with the input reference. The microprocessor tracks the new clock for a predetermined number of error samples in the wideband mode and statistically estimates, from the samples, the frequency of the input. After the frequency estimation, the microprocessor controls the loop VCO to output the computed frequency and switches to the narrow band tracking mode.

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First Claim