Importance

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Abstract

In a multiprocessor system, including a first processor, a second processor, a main memory (otherwise termed a Basic Storage Module - BSM), and a control circuit (termed BSM controls), the first processor may attempt to locate specific data in its cache and fail to locate this data. The first processor will query the cache of the second processor in an attempt to locate the specific data. If the data is located, an indication of the existence of the data in the cache of the second processor is sent and stored in a status register associated with the second processor. As a result, preliminary steps have been taken to 'flush' or move the data from the cache of the second processor to the BSM in order for the first processor to utilize the data. However, prior to the flush operation, it is necessary for the second processor to synchronize its clocks with the clocks of the BSM controls. When this synchronization is complete, the data in the cache of the second processor is flushed or moved to the BSM. The status register associated with the second processor is cleared. The data is then utilized by the first processor in the execution of an instruction. The present invention is directed to the synchronization of the clocks of the second processor with the clocks of the BSM controls prior to flushing desired data from the cache of the second processor to the BSM.

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First Claim