Importance

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Abstract

A multilevel semiconductor integrated circuit is fabricated by providing a plurality of substrates having an epitaxial layer on one surface and a silicon oxide layer on the surface of the epitaxial layer. The substrates are sequentially stacked with the silicon oxide layers in contact and fused together. One substrate is retained as a support, and other substrates are removed by etching after the fusion of the silicon oxide layers, thereby leaving only the stacked epitaxial layers separated by silicon oxide. The stacked structure facilitates the vertical fabrication of CMOS transistor pairs sharing a common gate electrode in an epitaxial layer between the two transistors. Electrical isolation between the epitaxial layers is provided by the fused silicon oxide or by removing the silicon oxide and some of the silicon thereby forming a void between adjacent epitaxial layers. Circuit devices in the plurality of epitaxial layers are readily interconnected by forming conductive vias between the epitaxial layers.

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First Claim