Four transistor cross-coupled bitline content addressable memory
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United States of America Patent
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May 16, 1989
Issued Date -
N/A
app pub date -
Oct 26, 1987
filing date -
Nov 27, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A content addressable memory cell comprises two storage IGFETs connected between a Match line and respective bitlines. Stored potentials are applied to the gates of the IGFETs through Write IGFETs which are cross coupled to the bitlines. The cross-coupling results in a larger storage capacitance and reduced degenerative capacitive coupling. This improves the speed and noise immunity of the cell. The memory cell is fabricated with three primary levels: a lower level of semiconductor material in which the source, drain and channel of each FET is formed, a center level of conductive material in which the Match and Write lines and the gates of the FETs are formed and an upper level in which the bitlines are formed. The center and lower levels are interconnected at buried contacts.
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