Method of fabricating a tapered via hole in polyimide
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United States of America Patent
Stats
-
May 23, 1989
Issued Date -
N/A
app pub date -
May 21, 1987
filing date -
Sep 27, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of: disposing a layer of SiO.sub.2 on the polyimide layer and a layer of photoresist on the SiO.sub.2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO.sub.2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO.sub.2 ; and repeating the etching step and enlarging step a predetermined number of times.
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