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Abstract

A digital to analog converter including an R-2R ladder network receives digitally encoded sample signals in parallel through a set of chains of transistor switches, each chain having equal delay. The ladder network output impedance matches the characteristic impedance of a coaxial cable transmission line that couples the converter output to a utilization circuit. Output resistances of the switches which are connected to ladder network rung circuits are scaled in accordance with a predetermined algorithm to maintain symmetry of parallel connected resistive branches of the latter network seen at each rail terminal of the ladder. Three of the most significant bits of each input binary coded work are decoded to a bar code format before being coupled through the set of switch chains. Switch output conductances in the switch chains are scaled in accordance with a stage-to-stage conductance ratio F, and at selected stages of selected ones of the chains dummy-load switches are added to enable both conformance to that ratio and substantial equality of delay among all of the chains.

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First Claim