Semiconductor device with a wiring layer having good step coverage for contact holes

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United States of America Patent

PATENT NO 4833519
SERIAL NO

07049917

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Abstract

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A method and apparatus are disclosed for improving step coverage of a wiring layer of a semiconductor device especially at the contact holes thereof. The inside of the contact holes are covered by a polysilicon layer deposited by chemical vapor deposition (CVD), and selectively doped with impurities having the same conductivity type as the contact region which the polysilicon layer contacts at the bottom of the contact hole. The remaining part of the contact hole is buried with SiO.sub.2, and the wiring layer is formed on it. Since the step coverage of the material deposited by CVD is very good, the disconnection at the side walls of the contact hole is avoided. Further, short circuits caused by growth of spikes of eutectic of silicon and aluminum is also avoided. If the surface of the polysilicon layer is covered with a thin film of SiO.sub.2 or Si.sub.3 N.sub.4, the material to bury the contact hole may be replaced by other materials such as polysilicon or amorphous silicon. Further, a barrier layer may be provided between the wiring layer and the polysilicon layer. This prevents the migration of aluminum over the polysilicon, so that the reliability of the wiring is further improved. The barrier layer is made from a silicide of high melting point metal or the metal itself. This improves the conduction between the contact region and the wiring layer.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Higashimoto, Masayuki Kawasaki, JP 2 56
Kashiwagi, Shigeo Yokohama, JP 1 42
Kawano, Michiari Kawasaki, JP 10 338
Nakano, Jun Yokohama, JP 82 405
Shimizu, Osamu Yokohama, JP 127 1774

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