Hierarchical priority branch handling for parallel execution in a parallel processor

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United States of America Patent

PATENT NO 4833599
SERIAL NO

07041081

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Abstract

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In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

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Patent Owner(s)

Patent OwnerAddress
HEWLETT-PACKARD DEVELOPMENT COMPANY L P10300 ENERGY DRIVE SPRING TX 77389

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Colwell, Robert P Guilford, CT 40 2075
O'Donnell, John Guilford, CT 62 1334
Papworth, David B Guilford, CT 56 3029
Rodman, Paul K Madison, CT 11 916

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