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Abstract

A clock signal is transmitted to nodes of each of several interconnected circuits through a separate adjustable delay circuit, the time delay of each delay circuit being adjusted so that the clock signal arrives at each node at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor. The delay element monitor measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.

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First Claim